David Tweed
Electrical and Software Engineer
P.O.Box 442
Chelmsford, MA 01824-0442
dtweed@acm.org

Goals: To solve both large and small engineering problems using the most appropriate mix of hardware and software. To broaden my experience in the areas of analog and digital signal processing.

Experience Summary: Hardware design of digital, analog and microprocessor-based systems. Software design of both software tools for hardware and software development, and of embedded system firmware. Leadership of technical teams and writing of technical documentation.

Skillset Summary:

• FPGA development - Altera (now Intel), Actel (now Microchip), Xilinx, VHDL and Verilog, Modelsim/Questasim and Icarus Verilog simulators
• Communications protocols - T1, E1, ISDN, synchronous and asynchronous serial data, audio compression algorithms, video interconnects, USB, IIC, SPI
• Digital hardware - FPGAs and PLDs, microprocessors, microcontrollers, DSPs, memory and cache systems
• Analog hardware - PLLs for clock generation and recovery, RF receiver chips (AM, FM, TV), audio processing with opamps, high-performance A/D and D/A converters, switchmode power converters
• Other hardware - PCB layout, design for EMC
• Embedded firmware - assembly and C programming of microcontrollers (ARM, 68302, 8051, 6502, Z80, AVR, PIC), assembly and C/C++ programming of DSPs (ADSP-BF5xx, ADSP-21xx, ADSP-21065, TMS320C31), including development of device drivers
• Desktop software - Matlab/Octave, C/C++, Awk, Perl and Python programming of development tools, system modeling and simple applications
• Communications - writing technical papers and specifications, webmastering

Patents:

• US Pat. 7,411,378 - Filed May 9, 2005 - Embed, Inc., "Power factor controller that computes currents without measuring them "
• US Pat. application 10,777,158 - Filed Feb 13, 2004 - Video Delta, Inc., "Embedded video processing system"
• US Pat. 7,295,567 - Filed Apr 4, 2003 - Harris Corporation, "Audio signal rate adaptation method and system"
• US Pat. 5,892,771 - Filed Dec 11, 1996 - Intraplex Incorporated, "System for establishing a TDM information protocol over a communications path"
• US Pat. 5,818,769 - Filed Nov 26, 1996 - Intraplex Incorporated, "Dynamically variable digital delay line"

Employment History

March 2000 - present: self-employed, Lowell, MA

Hardware and Firmware Engineering Consultant I work part-time for various clients, helping them solve problems both in system design and in low-level hardware and software design. Specific projects include: Ongoing support of product line that switches, processes and records HD video. Image Stream Medical Ongoing support of FPGAs that directly control cooled IR image sensors. American Infrared Solutions FPGA modules to transport high-definition video over an ultra-wideband radio link. G5 Infrared Low-level drivers to support communication among multiple Blackfin DSPs on an image-processing board. Odenberg FPGA modules to support frame capture in a high-definition video pipeline. Image Stream Medical Power and USB hub, and system integration for various multi-camera aerial photography "pods". Geovantage FPGA modules for real-time video processing. Tenesix, Inc. Power management firmware for regulator modules used in supercomputer. Bel Power Products Low-level IIC driver firmware for TI TMS320C55xx DSP. Low-power serial digital audio mux/demux FPGA for battery operated device. Seven Woods Audio, Inc. Hybrid inertial and GPS attitude sensor for accurate antenna pointing on vehicles with high dynamics. Enpoint, LLC Real-time video processing system, including digital video pipeline in an FPGA and multiport DDR SDRAM video buffer. Video Delta, Inc. Video system design and switchmode power systems (regulators and power factor controller) for a novel LED-based information display. Embed, Inc. System-level design of a LEO satellite-based telematics system. Embed, Inc. Cost and manufacturability analysis of automobile audio entertainment systems. Gotuit Media Corp. Feasability study of a multiple-channel audio entertainment receiver. Gotuit Media Corp. A second-generation design for a system that uses GPS as a time and frequency reference for synchronizing multiple broadcast transmitters to provide extended coverage on a single frequency. Harris Intraplex. A flexible scheme for providing FEC (forward error correction) in a real-time T1/E1 audio link. Harris Intraplex. A system for providing precision frequency offsets for managing delays in T1/E1 networks. Harris Intraplex. Redesign of two Actel FPGAs in a complex data multiplexing module to correct design problems and provide enhanced robustness. Harris Intraplex. Experience with: Altera Stratix, Cyclone FPGAs (Verilog, VHDL, Modelsim) Analog Devices ADSP-BF5xx "Blackfin" DSP (hardware design, assembly and C++ programming) Microchip PIC and dsPIC microcontrollers (assembly and C programming) Actel ProASIC, ProASIC3 FPGAs (VHDL, Modelsim) Analog Devices ADSP-TS201S "TigerSHARC" DSP (hardware design, assembly and C++ programming) Microchip PIC and dsPIC microcontrollers (assembly and C programming) Xilinx Spartan, Spartan-II, Spartan3 FPGAs (using VHDL, Modelsim) Intel PXA-255 Xscale ARM-based processor (hardware design) Analog Devices ADSP-21xx DSP (hardware design, assembly and C programming) Actel ACT-1 and ACT-2 FPGAs (hardware design)

November 1999 - present: Circuit Cellar Ink, Vernon, CT

Project Editor I work part-time, doing technical proofreading of all materials published in the monthly print and online magazines. I am responsible for the Test Your Engineering Quotient column, a 4-question technical quiz published every other month. I also write the occasional feature article (see Publications, below). Specific tasks include: Proofreading all published materials for technical accuracy and consistency. Organizing 4 engineering questions and answers every other month. Maintaining an HTML index to the magazine that is used both on the Internet and on the archival CDROMs.

December 1997 - March 2000: Verance Corporation (formerly Aris Technologies, Inc.), Cambridge, MA

Senior Hardware Engineer I was responsible for design, development, and production issues for the hardware platforms associated with digital audio watermarking applications. This included writing specifications, managing vendors, doing circuit and PCB design as well as writing much of the support firmware for the PC, the Analog Device SHARC DSP and the 8051 microcontroller. Specific projects include: A proof-of-concept low-cost decoder based on the 6502 architecture. A general-purpose serial communications protocol for connecting PCs, DSPs, and microcontrollers. Broadcast monitoring system to be deployed in major broadcast markets throughout the US and abroad. AM/FM and TV tuner banks to support broadcast monitoring. Very inexpensive decoders for toy and "throw-away" applications. Experience with: Texas Instruments TMS320C31 DSP (assembly and C programmning) Analog Devices ADSP-21065L DSP (assembly and C programmning) 6502-family microprocessor (hardware design, assembly and C programming) 8051-family microcontroller (hardware design, assembly and C programming) Dallas One-Wire devices (device drivers for 8051, SHARC) 1655x-family UART (device drivers for 'C31, SHARC) Atmel AVR-family microcontroller (hardware design, assembly programming) IBM-compatible PC (Windows 95, Windows NT, QNX, Wind River, Linux and FreeBSD operating systems; C and Perl programming) PCB layout using PCBExpress tools. RF circuit design.

April 1991 - December 1997: Intraplex, Inc., Westford, MA

Engineering Technical Director (July 1996 - December 1997) I was responsible for the future technological development of the company, in cooperation with management, sales and marketing as well as major customers. This included defining the next-generation product architecture as well as handling the technical side of the company's strategic alliances with other manufacturers. Engineering Design Manager (October 1995 - July 1996) I was responsible for the technical management of the engineering department, overseeing three project engineers and two associate engineers, plus outside consultants. I was also responsible for formalizing the engineering processes as Intraplex worked toward ISO 9001 certification. Specific projects include: DV-400 wideband voice module for Access-60 PT/PR-D35x program audio modules with AES/EBU interface CM-10/MA-220 ISDN line interface module DV-600 wideband voice module for TDM-160 Experience with: ISO 9000 Management by objectives Microsoft Project Microsoft Access Netmanage ECCO Project Engineer (April 1991 - October 1995) I developed T1, E1 and ISDN telecommunications equipment requiring systems level design as well as detailed hardware and software design and implementation. Responsibilities include interfacing with the marketing and manufacturing departments, and writing technical documentation from functional specifications through implementation guidelines and test procedures. Specific projects include: microprocessor-based T1 and E1 line interfaces DSP-based high-speed synchronous serial interface Audio codec for ISDN Experience with: Actel ACT-1 and ACT-2 FPGA families (hardware design) Analog Devices ADSP-21xx DSP (hardware design, assembly and C programming) Motorola MC68302 microprocessor (hardware design, assembly and C programming) 8051-family microcontroller (hardware design, assembly and C programming) ADC, DAC, and PLL applications ISO/MPEG Audio compression Orcad Design Tools MS-DOS operating system, Windows environment (C, awk, and PERL programming) Mathcad for modeling and simulation

August 1984 - April 1991: Apollo Computer Inc., Chelmsford, MA (acquired by Hewlett-Packard in May of 1989)

Electrical Engineer I designed systems and subsystems related to 680x0-based engineering workstations, including MMU (memory management unit), primary and secondary cache memory, bus interfaces, and main memory. As my knowledge and experience grew, my responsibilies expanded until I became a kind of systems "guru" and the technical leader for the design of a 68040-based system, where I was responsible for the overall hardware design and oversaw the activities of four other engineers. I was also the primary interface to Motorola as we and they debugged the 68040 itself. I was also involved at various times in technology evaulation projects and market studies. Specific projects include: Reverse-mapped MMU design for 12.5 and 16 MHz 68020 General system debug for a 20 MHz 68020 VME-based computer, including forward-mapped MMU and primary cache Develop "viewboard" program to display Gerber photoplot data on workstation to assist hardware debug CPU support and secondary cache design for 25 and 33 MHz 68030 Technical leader of hardware design team for 25 MHz 68040 desktop workstation, including main memory design Experience with: 68020, 68030, and 68040 microprocessors (hardware design) High-speed SRAM and high-performance DRAM VME and PC/AT (ISA and EISA) bus hardware design Aegis, Domain OS, and Unix operating systems (Pascal, C, shell, and PERL programming) Mentor Graphics design and simulation tools ABEL software (from Data-IO) for PAL programming Interleaf document preparation software

June 1983 - July 1984: Norden Systems, Merrimack, NH

Electrical Engineer I developed hardware subsystems related to a military-grade computer based on the VAX architecture. Experience with: VAX hardware architecture Valid design tools

June 1980 - May 1983: Burroughs Corporation, Paoli, PA

Electrical Engineer I designed an upgrade to the main CPU of the Burroughs Scientific Processor. I helped to developed system-level designs for a high-speed parallel processor with sole responsibility for the hardware design. I designed an integrated circuit to be used in a digital display for a radar system as a means to learn IC design techniques. Experience with: NMOS integrated circuit design (UNIX-based tools) Design of memory, communication and processor systems for high-speed parallel processing MCP and Unix operating systems (Algol and C programming) Unix-based text processing tools (nroff, troff)

Publications

• "Designing Real-time Embedded Software Using State-machine Concepts", Circuit Cellar Ink magazine, December 1994.
• "DSP-Based Canadian Timecode Receiver" (2-part series), Circuit Cellar Ink magazine, June-July 1997.
• "Micro Series: Digital Processing in an Analog World" (3-part series), Circuit Cellar Ink magazine, October-December 1998.
  PDF files: Part 1 Part 2 Part 3
• "Micro Series: Fundamentals of Second-Order Systems" (3-part series), Circuit Cellar Ink magazine, January-March 2001.
• The Circuit Cellar Ink on-line index at http://www.dtweed.com/circuitcellar/index.htm
• "A Bootloader For Blackfin", Circuit Cellar Ink magazine, August 2008.
• "iMCU W7100 — Embedded Networking Made Simple", Circuit Cellar Ink magazine, Decenber 2009.

Education

1980 BSEE degree from University of Delaware, Newark, DE
Emphasis on digital systems and computers. GPA: 3.446/4.000

1994 IEEE lecture series on wavelets and their applications.
1996 IEEE lecture series on the Global Positioning System and its applications.

Citizenship

I am a native-born U.S. citizen. I held a U.S. Top Secret security clearance from 1982-1984.

Other Interests

Music, bicycling, amateur radio